Peer Reviewed Journal via three different mandatory reviewing processes, since 2006, and, from September 2020, a fourth mandatory peer-editing has been added.
This paper presents a low power and high speed 3D-DWT
(three-dimensional discrete wavelet transform) architecture
using stacked silicon dies for image compression of medical
images. The interconnections of stacked chips are based on
TSV (through silicon via) techniques. Its low power
operation is due to short signal paths between layers. The
area of 3D architecture is much smaller than that of 2D
counterpart having the same performance. Each
circuit/system layer can be optimized since it can be
fabricated using a different technology.
The 3D-DWT architecture consists of two processing
elements (PE): a PE-odd (processing elements-odd) and a
PE-even (processing elements-even) layer. Each layer
processes pixel data derived from rows of the y axis,
scanning from left to right side of the image data. Each layer
operates in parallel yielding high throughput. The
architecture can be used to compress medical image such as
X-ray, MRI, NRI, CT and endoscopy by processing images
frame by frame.
