Peer Reviewed Journal via three different mandatory reviewing processes, since 2006, and, from September 2020, a fourth mandatory peer-editing has been added.
Field-programmable gate arrays (FPGAs) which have many
advantages are used in various devices. Use of the FPGAs is not
only prototyping and verification of circuits but also an
important part of the commercial products. A CPU of hardcore
is required in the FPGAs. But it has a problem with the
architecture of the CPU is limited. The method of solving these
problems is developing a system on a chip (SoC) which is
equipped with FPGAs and a customized CPU. From the view
point of ease of design and shortening a design period,
development techniques on a register-transfer level (RTL) using
a standard cell library are essential. On the other hand, applying
this method without using a design technique has a problem in
terms of throughput. In this paper, a connection block for routing
using wave-pipeline technique is proposed to solve the
throughput problems. This block is evaluated, and it is shown
that it is useful for wave pipeline operation.
